A very serious problem in the area of semiconductor memories is power consumption.
The article of D. Cantarelli, A. Maurelli and L. Baldi, "A high-performance p-channel EPROM cell", ESSDERC 1987, Proceedings, pages 769-771, proposes a p-channel cell instead of an n-channel cell as in the well-established tradition for the manufacture of EPROM memory devices. This article underscores the various advantages of inversion of the type of conductivity of the elements making up the traditional structure of the EPROM memory cell, among which is that of low power consumption in the writing phase.
In recent years, electrically programmable and erasable non-volatile memories such as FLASH and EEPROM memories have spread widely, in particular for applications where low power consumption is a very important requisite.
Applying the lesson of the above mentioned article to these types of memories, what is obtained is a new type of electrically programmable and erasable non-volatile memory cell whose cross section is shown in the annexed FIG. 1. But the gate oxide in this case is thinner to allow conduction by tunnel effect and can be 8 nm to 9 nm for EEPROM memories and 10 nm to 12 nm for FLASH memories.
The memory cell of FIG. 1 consists of a double-gate MOS transistor and comprises a type-n zone 1, two p-type regions 2 and 3 implemented in the zone 1 and separated from each other by a spacing, and a double gate structure implemented over the zone 1 opposite the spacing. The double-gate structure comprises an insulated gate 5 and a connected gate 4 superimposed on and insulated from the gate 5 and inserted in a layer 6 of insulating material. The region 2 extends beneath the insulated gate 5. The space 9 of the region 2 bordering on the zone 1 is normally doped more lightly than the remaining space. FIG. 1 also shows two layers 7 and 8 of insulating material which leave two openings over the regions 2 and 3 respectively for optional contacts. This structure corresponds to one of traditional type such as, e.g., that illustrated in FIG. 7 of U.S. Pat. No. 4,142,926, except for the type of conductivity of the constituting elements.
As known, the space 9 is very important in the erasing phase of the cell to permit passage of charges from the insulated gate 5 to the region 2, which corresponds to the source region of the MOS transistor.
From U.S. Pat. No. 4,203,158 is known a more sophisticated solution to this problem, and which, however, implies again superimposing (more generally an approach) between the insulated gate and the source region.
Implementation of this superimposition involves considerable complication in the production process in terms both of number of masks required and production time. Furthermore, at high integration levels, e.g. 0.5-1.0 u technologies, the space 9 (which can be an extension of e.g. 0.15-0.3 u beneath the insulated gate) considerably affects the minimal size of the cell.
A process of this type and which also allows simultaneous manufacture of FLASH and EEPROM memory cells is illustrated in U.S. Pat. No. 4,957,877. A discussion of these problems and their possible solutions both as to structure and as to process is found in U.S. Pat. No. 5,102,815.